1. Field of the Invention
The present invention relates to a semiconductor device comprising a data bus including data lines transmitting data, and a plurality of data input/output terminals for inputting/outputting transmission data of the data bus from/to outside.
2. Description of Related Art
In recent years, increases in capacity and speed have been achieved in semiconductor devices such as DRAM (Dynamic Random Access Memory) that are capable of storing data in a plurality of memory cells, and thus a configuration is required in which transmission data can be transferred with high speed from/to outside through a data bus arranged in a high density. For example, assuming a configuration shown in later-described FIGS. 1 to 4 as a general configuration of the DRAM, data read out from a memory cell is transmitted to a data bus DB1 through an internal circuit, and is transmitted from the data bus DB1 to DQ pads in synchronization with a high-speed clock so as to be outputted to outside. Since the DQ pads are arranged in a manner as shown in a later-described DQ region R4 of FIG. 6 (DQ pads 0 to 15), for example, there are data lines extending from the data bus DB1 to a plurality of DQ pads. In this case, if high-speed data transfer is performed in a state where a plurality of data lines are arranged close to one another, there is a possibility that transmission quality may be deteriorated due to noise or the like caused by coupling between adjacent data lines. Therefore, wiring structures for improving the transmission quality of the plurality of data lines arranged in parallel have been conventionally proposed (for example, refer to Patent Reference 1)    [Patent Reference 1] Japanese Patent Application Laid-open No. 2009-231513 (U.S. Pat. No. 7,923,809)
FIG. 17 shows a general structural example for arranging the plurality of data lines of the data bus DB1, which is a cross-sectional structural view showing a portion near a left end of a DQ region R4 (FIG. 1) of the data bus DB1. That is, a plurality of data lines D of the data bus DB1 having the same width are arranged in parallel with the same spacing in an upper wiring layer M2, and a coupling capacitance Cc exists between adjacent two data lines. Meanwhile, lines having a wide width that are connected to power supplies or the like are arranged in a lower wiring layer M1 for a countermeasure against noise. However, it is difficult to sufficiently suppress the coupling capacitance Cc only by this countermeasure.
Here, a problem associated with the high-speed data transfer through the data bus DB1 will be described using FIGS. 18A and 18B. FIG. 18A shows a transmission circuit by which the data bus DB1 is modeled. FIG. 18B shows a waveform of an input signal A, a waveform of a transmission signal B, and waveforms of an output signal C, regarding a focused line at the center in FIG. 18A. The input signal A is subject to crosstalk affected by the coupling capacitance Cc from adjacent two lines on both sides, which results in that the waveform of the transmission signal B is rounded off. At this point, the lines of the data bus DB1 operate at the same timing, and their levels (HIGH/LOW) randomly change. Therefore, following three states of the adjacent lines on both sides can be considered:
(State-1) both adjacent lines change with the same phase as the focused line.
(State-2) One of the adjacent lines change with the same phase as the focused line, and the other thereof changes with an opposite phase to the focused line.
(State-3) Both adjacent lines change with the opposite phase to the focused line. Thereby, the transmission waveform B behaves differently in accordance with the above three states. That is, timings at which the transmission waveform B rises to HIGH include three timings t1, t2 and t3 corresponding to the state-1, state-2 and state-3, respectively, as shown in an enlarged part on the right side of FIG. 18B. As a result, different delays Δt occur in the waveforms of the output signal C in accordance with the three states, as shown on the lower side of FIG. 18B. Assuming that this phenomenon occurs, a circuit that receives data from the focused line needs to be designed to permit that the timings of the states are deviated from one another. However, designing in such a manner is difficult to achieve under an environment of high-speed operations as fast as clocks. Therefore, it is desirable to reduce the coupling capacitance Cc between adjacent data lines of the data bus DB1 by other measures. A first measure for reducing the coupling capacitance Cc between adjacent data lines of the data bus DB1 is to widen a gap between the data lines D based on the structure of FIG. 17. By widening the gap in this manner, the coupling capacitance Cc of FIG. 17 becomes small, but a lager layout area is required corresponding to widening the gap. Therefore, an increase in chip size is brought about, and a sufficient suppression effect of the crosstalk cannot be obtained. FIG. 19 is a structural diagram for explaining a second measure for reducing the coupling capacitance Cc between adjacent data lines of the data bus DB1. As shown in FIG. 19, by arranging shield lines S between respective adjacent data lines D, it is possible to sufficiently reduce the coupling capacitance Cc so as to suppress the crosstalk. However, in the second measure, when the number of data lines D and the arrangement gap therebetween are assumed to be the same as those in FIG. 17, the total number of lines simply doubles by adding the shield lines S, and thus an increase in chip size is inevitable. FIG. 20 is a structural diagram for explaining a third measure between the first and second measures. As shown in FIG. 20, the shield lines S are arranged in both sides of each pair of adjacent data lines D. Thereby, the suppression effect of the crosstalk can be larger than the first measure, and the layout area can be smaller than the second measure. However, a larger layout area is required in comparison with FIG. 17, and thus an increase in chip size is also brought about in this case.
In this manner, when achieving a wiring structure of the data bus used in the high-speed data transmission in the conventional semiconductor device, it has been difficult to achieve a design that satisfies both requirements of excellent transmission performance and prevention of an increase in chip size.